1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to, a semiconductor memory device capable of controlling an address access time tAA.
2. Discussion of Related Art
In a semiconductor memory device such as a pseudo SRAM, speed of a sense generator signal sg, as a control signal of a bitline sense amplifier, and a precharge signal pcg is an important parameter determining an address access time tAA.
FIG. 1 is a schematic block diagram illustrating a row path of a semiconductor memory device.
An address inputted through an input buffer 10 is stored in a register 20, and a part of addresses is inputted in a state machine 30. The state machine 30 generates a code for controlling a chip select signal /CS, a precharge signal pcg, a sense generator signal sg, a column address strobe signal /CAS, and a row address strobe signal /RAS. A control path 50 activates a cell block 60 according to signals supplied from the register 20, the state machine 30, and a refresh control unit 40.
FIG. 2 is a waveform diagram illustrating a bitline sensing operation.
The sense generator signal sg maintains high level by the state machine 30, and then when the precharge signal pcg is enabled to high state, the sense generator signal sg becomes low state, which results in that a potential of a bitline becomes Vcore/2. When the sense generator signal sg rises to high state and the column address select signal Yi is enabled, a potential of a corresponding bitline BL rises to a core voltage Vcore, while a potential of a bitline /BL falls down to a ground potential VSS.
FIG. 3 is a block diagram illustrating a control path of a row path in the conventional art. It will be explained with reference to FIG. 4.
A chip is enabled in a period that the chip select signal /CS1 is low state and then starts to receive an address ADD. After a row active signal rowact is enabled, the sense generator signal sg is enabled. The sense generator signal. sg enables the precharge signal pcg. The sense generator signal sg determines an enabling timing of sense amplifier control signals, i.e., an rto (generally high voltage) and an sb (generally a ground voltage), as a signal for delaying a time as long as a bitline sense amplifier (now shown) operates after the row active signal rowact is enabled. The precharge signal pcg determines a disabling timing of the rto and the sb.
That is, when the sense generator signal sg is enabled after the row active signal rowact is enabled, the bitline sense amplifier is operated, which leads to output a developed data DO (as shown in FIG. 4). When the prechage signal pcg is enabled, the sense generator signal sg is disabled.
As aforementioned, the conventional control path has a default scheme for outputting data by 1) when the address ADD is enabled, the row active signal rowact is enabled, 2) the precharge signal pcg is enabled, 3) the previous (or existing) sense generator signal sg is disabled, and 4) the sense generator signal sg is enabled again. It will be performed the same operation as the aforementioned operation in a refresh mode. Data is outputted by those sequential operations. However, in the conventional art, there is no method for analyzing a time taken by data outputting after an address is inputted, namely, the address access time tAA, by each period.